IDT70V3589 Datasheet | IDT

Features : - True Dual-Port memory cells which allow simultaneous access of the same memory location - High-speed data access - mercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) - Industrial: 4.2ns (133MHz) (max.) - Selectable Pipelined or Flow-Through output mode - Counter enable and repeat features - Dual chip enables allow for depth expansion without additional logic - Full synchronous operation on both ports - 6ns cycle time, 166MHz operation (12Gbps bandwidth) - Fast 3.6ns clock to data out - 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz - Data input, address, byte enable and control registers - Self-timed write allows fast cycle time - Separate byte controls for multiplexed bus and bus matching patibility - Dual Cycle Deselect (DCD) for Pipelined Output mode - LVTTL- patible, 3.3V (±150m V) power supply for core - LVTTL patible, selectable 3.3V (±150m V) or 2.5V (±100m V) power supply for I/Os and control signals on each port - Industrial temperature range (-40°C to +85°C) is available at 133MHz. - Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fp BGA), and 256-pin Ball Grid Array (BGA) - Supports JTAG features pliant with IEEE 1149.1 - Green parts available, see ordering information Note; the information regarding recently obsoleted parts is included in this datasheet for customer convenience. Please see the Orderable Parts Table for the current, active part list. Functional Block Diagram BE3L BE3R BE2L BE2R BE1L BE1R BE0L BE0R FT/PIPEL R/WL CE0L CE1L 0a 1a 1/0 a 0b 1b b 0c 1c...