IDT49FCT805A
FEATURES
:
- 0.5 MICRON CMOS Technology
- Guaranteed low skew < 700ps (max.)
- Low duty cycle distortion < 1ns (max.)
- Low CMOS power levels
- TTL patible inputs and outputs
- Rail-to-rail output voltage swing
- High drive: -24m A IOH, +64m A IOL
- Two independent output banks with 3-state control
- 1:5 fanout per bank
- "Heartbeat" monitor output
- Available in SSOP and SOIC packages
DESCRIPTION
:
The 49FCT805 is a non-inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a standard TTL patible input. These devices feature a “heart-beat” monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and plies with the output specifications in this document.
The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS inputs.
FUNCTIONAL BLOCK DIAGRAM
OEA INA
INB...
