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9FGL0651 - 6-Output 3.3V PCIe Clock Generator

Download the 9FGL0651 datasheet PDF. This datasheet also covers the 9FGL0641 variant, as both devices belong to the same 6-output 3.3v pcie clock generator family and are provided as variant models within a single manufacturer datasheet.

General Description

The 9FGL0641 / 9FGL0651 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family.

The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off.

4 Common Clocked architectures

Key Features

  • Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:.
  • 9FGL0641 default Zo = 100Ω.
  • 9FGL0651 default Zo = 85Ω.
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support.
  • See AN-891 for easy AC-coupling to other logic families Key Specifications.
  • PCIe Gen1.
  • 4 CC compliant; Gen2.
  • 3 SRIS compliant.
  • DIF cycle-to-cycle jitter < 50ps.
  • DIF output-.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (9FGL0641-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 9FGL0651
Manufacturer IDT
File Size 319.72 KB
Description 6-Output 3.3V PCIe Clock Generator
Datasheet download datasheet 9FGL0651 Datasheet

📁 Similar Datasheet

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9FGL0641D 3.3V PCIe Gen1-6 Clock Generator Renesas
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Other Datasheets by IDT

Part Number Description
9FGL06 6-output 3.3V PCIe Clock Generator
9FGL0641 6-Output 3.3V PCIe Clock Generator
9FGL02 2-output 3.3V PCIe Clock Generator
9FGL0241 2-Output 3.3V PCIe Clock Generator
9FGL0251 2-Output 3.3V PCIe Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
6-Output 3.3V PCIe Clock Generator 9FGL0641 / 9FGL0651 Datasheet Description The 9FGL0641 / 9FGL0651 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family. The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL0641 / 9FGL0651 supports PCIe Gen1–4 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. Typical Applications ▪ Servers/High-Performance Computing/Accelerators ▪ Storage ▪ Embedded Systems/Industrial Control Output Features ▪ Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs: • 9FGL0641 default Zo = 100Ω • 9FGL0651 default Zo = 85Ω ▪ One 3.