Datasheet4U Logo Datasheet4U.com

9DB306 - PCI Express Jitter Attenuator

Description

The 9DB306 is a high performance 1-to-6 Differential-toLVPECL Jitter Attenuator designed for use in PCI Express™ systems.

In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer.

Features

  • Six differential LVPECL output pairs.
  • One differential clock input.
  • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • Maximum output frequency: 140MHz.
  • Input frequency range: 90MHz - 140MHz.
  • VCO range: 450MHz - 700MHz.
  • Output skew: 135ps (maximum).
  • Cycle-to-Cycle jitter: 30ps (maximum).
  • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical).
  • 3.3V operating supply.

📥 Download Datasheet

Datasheet Details

Part number 9DB306
Manufacturer IDT
File Size 203.66 KB
Description PCI Express Jitter Attenuator
Datasheet download datasheet 9DB306 Datasheet

Full PDF Text Transcription

Click to expand full text
PCI Express Jitter Attenuator 9DB306 Data Sheet GENERAL DESCRIPTION The 9DB306 is a high performance 1-to-6 Differential-toLVPECL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile.
Published: |