9DB1933
Description
The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards patible to PCIe Gen2 and Gen1.
Key Features
- 19 - 0.7V current mode differential HCSL output pairs Features/Benefits
- 8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment
- 11 dedicated and 3 group OE# pins/Hardware control of the outputs
- PLL or bypass mode/PLL can dejitter ining clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
