ICS548-03 Low Skew Clock Inverter and Divider
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• Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low s.
that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be u.
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