HYMP125U72CP8-C4 Datasheet, Hynix Semiconductor

* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Ban.

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Jul. 2008 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS C4.