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HYMD216M726A6-K - Unbuffered DDR SO-DIMM

Download the HYMD216M726A6-K datasheet PDF. This datasheet also covers the HYMD216M726A6-H variant, as both devices belong to the same unbuffered ddr so-dimm family and are provided as variant models within a single manufacturer datasheet.

Description

Hynix HYMD216M726A(L)6-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx72 high-speed memory arrays.

Features

  • 128MB (16M x72) Unbuffered DDR SO-DIMM ECCbased on 16Mx16 DDR SDRAM JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz/166MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Dat.

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Note: The manufacturer provides a single datasheet file (HYMD216M726A6-H_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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16Mx72 bits Unbuffered DDR SO-DIMM HYMD216M726A(L)6-J/M/K/H/L DESCRIPTION Hynix HYMD216M726A(L)6-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216M726A(L)6-J/M/K/H/L series consists of five 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD216M726A(L)6-J/M/K/H/L series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD216M726A(L)6-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs.
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