HY5DU281622LT Overview
and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
HY5DU281622LT Key Features
- VDD, VDDQ = 2.6V +/- 0.1V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK,
- data transaction aligned to bidirectional data strobe (DQS)
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Progr
- Auto refresh and self refresh supported . LDQS) per each x8 I/O
- tRAS lock out function supported Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (c
- 4096 refresh cycles / 64ms DQ)
- JEDEC standard 400mil 66pin TSOP-II with 0.65mm On chip DLL align DQ and DQS transition with CK pin pitch transition
- Full and Half strength driver option controlled by DM mask write data-in at the both rising and falling EMRS edges of th
- Note : D of speed indicates DDR400
