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HY57V28820HCLT - 4Banks x 4M x 8bits Synchronous DRAM

This page provides the datasheet information for the HY57V28820HCLT, a member of the HY57V28820HCT 4Banks x 4M x 8bits Synchronous DRAM family.

Description

The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V28820HC(L)T is organized as 4banks of 4,194,304x8.

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Datasheet Details

Part number HY57V28820HCLT
Manufacturer SK Hynix
File Size 236.80 KB
Description 4Banks x 4M x 8bits Synchronous DRAM
Datasheet download datasheet HY57V28820HCLT Datasheet
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HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM 0.1 : Hynix Change 0.2 : Burst read single write mode correction Rev. 0.2 / Aug. 2001 1 HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM DESCRIPTION The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820HC(L)T is organized as 4banks of 4,194,304x8. HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
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