HMT125U7BFR8C
Description
Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address.
Key Features
- Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment
- Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(1Rank of x8) 3.3 1GB, 128Mx72 ECC Module(1Rank of x8) 3.4 2GB, 256Mx64 Module(2Rank of x8) 3.5 2GB, 256Mx72 ECC Module(2Rank of x8)
- Address Mirroring Feature 4.1 DRAM Pin Wiring for Mirroring
- Absolute Maximum Ratings 5.1 Absolute Maximum DC Ratings 5.2 Operating Temperature Range
- AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions 6.2 DC & AC Logic Input Levels 6.2.1 For Single-ended Signals 6.2.2 For Differential Signals 6.2.3 Differential Input Cross Point 6.3 Slew Rate Definition 6.3.1 For Ended Input Signals 6.3.2 For Differential Input Signals 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels 6.4.2 Differential DC & AC Output Levels 6.4.3 Single Ended Output Slew Rate 6.4.4 Differential Ended Output Slew Rate 6.5 Overshoot/Undershoot Specification 6.6 Input/Output Capacitance & AC Parametrics 6.7 IDD Specifications & Measurement Conditions
- Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density 7.2 DDR3 Standard speed bins and AC para
- DIMM Outline Diagram 8.1 512MB, 64M
