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HMA451S6AFR8N - DDR4 SDRAM SO-DIMM

Download the HMA451S6AFR8N datasheet PDF. This datasheet also covers the HMA425S6AFR6N variant, as both devices belong to the same ddr4 sdram so-dimm family and are provided as variant models within a single manufacturer datasheet.

Description

SK hynix Unbuffered Small Outline DDR4 SDRAM DIMMs (Unbuffered Small Outine Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices.

Features

  • Power Supply: VDD=1.2V (1.14V to 1.26V).
  • VDDQ = 1.2V (1.14V to 1.26V).
  • VPP - 2.5V (2.375V to 2.75V).
  • VDDSPD=2.25V to 3.6V.
  • Functionality and operations comply with the DDR4 SDRAM datasheet.
  • 16 internal banks.
  • Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif- ferent bank group accesses are available.
  • Data transfer rates: PC4-2400,PC4-2133, PC4-1866, PC4-1600.
  • Bi-Dire.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HMA425S6AFR6N-HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
HMA451S7AFR8N DDR4 SDRAM SO-DIMM
HMA41GS6AFR8N DDR4 SDRAM SO-DIMM
HMA41GS7AFR8N DDR4 SDRAM SO-DIMM
HMA425S6AFR6N DDR4 SDRAM SO-DIMM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
260pin DDR4 SDRAM SODIMM DDR4 SDRAM SO-DIMM Based on 4Gb A-die HMA425S6AFR6N HMA451S6AFR8N HMA451S7AFR8N HMA41GS6AFR8N HMA41GS7AFR8N *SK hynix reserves the right to change products or specifications without notice. Rev. 1.7 / Mar.2016 1 Revision History Revision No. 0.1 0.2 0.21 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 History Initial Release Changed development plan Module dimension Update (Detail-A : 0.125->1.125) IDD Specification update Changed maximum VDDSPD from 2.75V to 3.6 Revised CWL value Corrected Pin Assignments Added development plan (1Rx16) Changed Module Dimension Updated JEDEC Specification Deleted Speed Grade Table Updated IDD Specification(1Rx16) Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns) Updated JEDEC Specification Draft Date Dec.2014 Jan.2015 Feb.2015 May.2015 Jun.
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