H57V1262GTR i/o equivalent, 128mb synchronous dram based on 2m x 4bank x16 i/o.
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* Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead Free Package) All inputs and output.
which require wide data I/O and high bandwidth. H57V1262GTR series is organized as 4banks of 2,097,152 x 16. H57V1262GTR.
and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57.
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