Datasheet4U Logo Datasheet4U.com

H55S1222EFP-A3E - 128MBit MOBILE SDR SDRAMs based on 1M x 4Bank x32 I/O

This page provides the datasheet information for the H55S1222EFP-A3E, a member of the H55S1222EFP-60E 128MBit MOBILE SDR SDRAMs based on 1M x 4Bank x32 I/O family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

📥 Download Datasheet

Datasheet preview – H55S1222EFP-A3E

Datasheet Details

Part number H55S1222EFP-A3E
Manufacturer Hynix Semiconductor
File Size 1.12 MB
Description 128MBit MOBILE SDR SDRAMs based on 1M x 4Bank x32 I/O
Datasheet download datasheet H55S1222EFP-A3E Datasheet
Additional preview pages of the H55S1222EFP-A3E datasheet.
Other Datasheets by Hynix Semiconductor

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com 128MBit MOBILE SDR SDRAMs based on 1M x 4Bank x32 I/O Specification of 128M (4Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 1,048,576 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jun. 2008 1 www.DataSheet4U.com 1128Mbit (4Mx32bit) Mobile SDR Memory H55S1222EFP Series Document Title 4Bank x 1M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 Initial Draft - Define IDD specification -. Correct Temp range(p.9) -. Modify IDD Values(p.11 & p.12) History Draft Date Sep. 2007 Feb. 2008 Remark Preliminary Preliminary 1.0 Jun. 2008 Rev 1.0 / Jun. 2008 2 www.DataSheet4U.
Published: |