Datasheet4U Logo Datasheet4U.com

HY5DU281622FTP - 128Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333) VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400 and 400Mbps/pin product) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data.

📥 Download Datasheet

Datasheet preview – HY5DU281622FTP

Datasheet Details

Part number HY5DU281622FTP
Manufacturer Hynix
File Size 288.17 KB
Description 128Mb DDR SDRAM
Datasheet download datasheet HY5DU281622FTP Datasheet
Additional preview pages of the HY5DU281622FTP datasheet.

📁 Similar Datasheet

  • HY5DU281622 - 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
  • HY5DU281622AT - (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
  • HY5DU281622AT-6 - 128M(8Mx16) DDR SDRAM (Hynix Semiconductor)
  • HY5DU281622DT - (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
  • HY5DU281622ET - 128M(8Mx16) GDDR SDRAM (Hynix Semiconductor)
  • HY5DU281622LT - (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
  • HY5DU281622LT - (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
  • HY5DU281622LT-H - 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
  • HY5DU281622LT-K - 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
  • HY5DU281622LT-L - 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
Other Datasheets by Hynix

Full PDF Text Transcription

Click to expand full text
128Mb DDR SDRAM HY5DU281622FTP www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.03 /Jun. 2006 1 HY5DU281622FT(P) Series Revision History Revision No. 0.01 0.02 0.03 First version for internal review State Diagram modified Defined : IDD value History Draft Date Feb. 2006 Apr. 2006 Apr. 2006 Remark www.DataSheet4U.com Rev. 0.03 /Jun. 2006 2 HY5DU281622FT(P) Series DESCRIPTION The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Published: |