HM621400H Datasheet | Hitachi Semiconductor

Description The HM621400H is a 4-Mbit high speed static RAM organized 4-Mword × 1-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM621400H is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features - Single 5.0 V supply : 5.0 V ± 10 % - Access time 10/12/15 ns (max) - pletely static memory  No clock or timing strobe required - Equal access and cycle times - Directly TTL patible  All inputs and outputs - Operating current: 200/180/160 m A (max) - TTL standby current: 70/60/50 m A (max) - CMOS standby current: 5 m A (max) : 1.2 m A (max) (L-version) - Data retension current: 0.8 m A (max) (L-version) - Data retension voltage: 2 V (min) (L-version) - Center VCC and VSS type pinout HM621400H Series Ordering Information Type No. HM621400HJP-10 HM621400HJP-12 HM621400HJP-15 HM621400HLJP-10 HM621400HLJP-12 HM621400HLJP-15 Access time 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns Package 400-mil 32-pin plastic SOJ (CP-32DB) Pin Arrangement HM621400HJP/HLJP Series A0 A1 A2 A3 A4 A5 CS VCC VSS Din WE A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A21 A20 A19 A18 A17 A16 OE VSS VCC Dout A15 A14 A13 A12 A11 NC HM621400H Series Pin Description Pin name A0 to A21 Din Dout CS OE WE VCC VSS NC Function Address input Data input Data output Chip select Output enable Write enable Power supply Ground No connection Block Diagram (LSB) A2 A18 A8 A12 A17 A3 A7 A6 (MSB) Din Column I/O Column decoder CS Dout Row decoder Memory matrix 256 rows × 64 columns × 256 blocks × 1 bit (4,194,304 bits) Internal voltage generater VCC VSS A11 A9 A10A20 A21 A0 A13 A14 A15 A1 A19 A16 A4 A5 CS WE OE CS (LSB) (MSB) HM621400H Series Operation Table CS H L L L L...