Datasheet4U Logo Datasheet4U.com

GS881E36CGT-xxxIV - 9Mb Sync Burst SRAMs

Download the GS881E36CGT-xxxIV datasheet PDF. This datasheet also covers the GS881E18CT-xxxIV variant, as both devices belong to the same 9mb sync burst srams family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Linear Burst Order (LBO) input. The Burst function need not.
  • FT pin for user-configurable flow through or pipeline operation.
  • Dual Cycle Deselect (DCD) operation be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads.
  • IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by.
  • 1.8 V or 2.5 V +10%/.
  • 10% core power supply the user via the.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS881E18CT-xxxIV-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS881E36CGT-xxxIV
Manufacturer GSI Technology
File Size 326.59 KB
Description 9Mb Sync Burst SRAMs
Datasheet download datasheet GS881E36CGT-xxxIV Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
GS881E36AD Synchronous Burst SRAMs GSI
GS88118 (GS88118 / GS88136T) Sync Burst SRAMs GSI
GS88118A (GS88118A - GS88136A) Synchronous Burst SRAMs GSI
GS88118B (GS88118B - GS88136B) Sync Burst SRAMs GSI
GS88132A (GS88118A - GS88136A) Synchronous Burst SRAMs GSI

Other Datasheets by GSI Technology

Part Number Description
GS881E36CGD-xxxIV 9Mb Sync Burst SRAMs
GS881E36CD-xxxIV 9Mb Sync Burst SRAMs
GS881E36CT-xxxIV 9Mb Sync Burst SRAMs
GS881E32AD Synchronous Burst SRAMs
GS881E32CD-xxxIV 9Mb Sync Burst SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS881E18/32/36C(T/D)-xxxIV 100-Pin TQFP & 165-bump BGA 512K x 18, 256K x 32, 256K x 36 Industrial Temp 9Mb Sync Burst SRAMs 250 MHz–150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Features Linear Burst Order (LBO) input. The Burst function need not • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads • IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by • 1.8 V or 2.5 V +10%/–10% core power supply the user via the FT mode pin (Pin 14). Holding the FT mode • 1.8 V or 2.