GS88037CT-xxxV datasheet, sram equivalent, GSI Technology

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Features and benefits

* Single Cycle Deselect (SCD) operation
* 1.8 V or 2.5 V +10%/
–10% core power supply
* 1.8 V or 2.5 V I/O supply
* LBO pin for Linear or I.

Application

* JEDEC-standard 100-lead TQFP package
* RoHS-compliant 100-lead TQFP package available Functional Description A.

Description

Applications The GS88037CT-xxxV is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performanc.

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