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GS8662T09BD - 72Mb SigmaDDR-II Burst of 2 SRAM

Download the GS8662T09BD datasheet PDF. This datasheet also covers the GS8662T08BD variant, as both devices belong to the same 72mb sigmaddr-ii burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Simultaneous Read and Write SigmaDDR™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36, x18 and x9) and Nybble Write (x8) function.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for pr.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8662T08BD-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8662T09BD
Manufacturer GSI Technology
File Size 356.45 KB
Description 72Mb SigmaDDR-II Burst of 2 SRAM
Datasheet download datasheet GS8662T09BD Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8662T08BD 72Mb SigmaDDR-II Burst of 2 SRAM
GS8662T18BD 72Mb SigmaDDR-II Burst of 2 SRAM
GS8662T36BD 72Mb SigmaDDR-II Burst of 2 SRAM
GS8662TT06BD 72Mb SigmaDDR-II+ Burst of 2 SRAM
GS8662TT06BGD 72Mb SigmaDDR-II+ Burst of 2 SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS8662T08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaDDR-IITM Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36, x18 and x9) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.