GS8662S18E-167 sram equivalent, ddr sigmasio-ii sram.
* Simultaneous Read and Write SigmaSIO™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Write controls sampled at d.
where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular .
Table Symbol
SA NC R/W NW0
–NW1 BW0
–BW1 BW0
–BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ Dn Qn VDD VDDQ VSS
Description
Synchronous Address Inputs No Connect Read/Write Contol Pin Synchronous Nybbl.
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