Description
Table Symbol
SA NC R/W NW0.
NW1 BW0.
BW1 BW0.
BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ Dn Qn VDD VDDQ VSS
Description
Synchronous Address Inputs No Connect Read/Write Contol Pin Synchronous Nybble Writes Synchronous Byte Writes Synchronous Byte Writes Input Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Input Clock Output Clock DLL Disable Synchronous Load Pin Output.
Features
- Simultaneous Read and Write SigmaSIO™ Interface.
- JEDEC-standard pinout and package.
- Dual Double Data Rate interface.
- Byte Write controls sampled at data-in time.
- DLL circuitry for wide output data valid window and future frequency scaling.
- Burst of 2 Read and Write.
- 1.8 V +100/.
- 100 mV core power supply.
- 1.5 V or 1.8 V HSTL Interface.
- Pipelined read operation.
- Fully coherent read and write pipelines.
