Description
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input.
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0.
BW3
Synchronous Byte Writes
Input Active Low
NW0.
NW1
Synchronous Nybble Writes
Input
Active Low (x8 only)
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input.
TDI
Test Data Input
Input.
TCK
Test Clock Input
Input.
TDO
Tes.
Features
- 2.0 Clock Latency.
- Simultaneous Read and Write SigmaQuad™ Interface.
- JEDEC-standard pinout and package.
- Dual Double Data Rate interface.
- Byte Write controls sampled at data-in time.
- Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs.
- Burst of 2 Read and Write.
- 1.8 V +100/.
- 100 mV core power supply.
- 1.5 V or 1.8 V HSTL Interface.
- Pipelined read operation.
