GS8662QT37BD
Features
- 2.0 Clock Latency
- Simultaneous Read and Write Sigma Quad™ Interface
- JEDEC-standard pinout and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
- Burst of 2 Read and Write
- 1.8 V +100/- 100 m V core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- Data Valid Pin (QVLD) Support
- IEEE 1149.1 JTAG-pliant Boundary Scan
- 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
- Ro HS-pliant 165-bump BGA package available
Sigma Quad™ Family Overview
The GS8662QT07/10/19/37BD are built in pliance with the Sigma Quad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662QT07/10/19/37BD Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to...
