Datasheet4U Logo Datasheet4U.com

GS8662Q36E-250 - 72Mb SigmaQuad-II Burst

Download the GS8662Q36E-250 datasheet PDF. This datasheet also covers the GS8662Q08E-300 variant, as both devices belong to the same 72mb sigmaquad-ii burst family and are provided as variant models within a single manufacturer datasheet.

General Description

Table Symbol SA NC R W BW BW0 BW3 NW0 NW1 K K C C TMS TDI TCK TDO VREF ZQ Qn Dn Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Write Synchronous Byte Write

Key Features

  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.
  • ZQ pin for programmable output drive strength.
  • IEEE 1149.1 JTAG-co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8662Q08E-300_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8662Q36E-250
Manufacturer GSI Technology
File Size 2.07 MB
Description 72Mb SigmaQuad-II Burst
Datasheet download datasheet GS8662Q36E-250 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary GS8662Q08/09/18/36E-300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available 72Mb SigmaQuad-II Burst of 2 SRAM 300 MHz–167 MHz 1.8 V VDD 1.8 V and 1.