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GS8640Z18T-250 Datasheet Preview

GS8640Z18T-250 Datasheet

72Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS8640Z18/36T-300/250/200/167
100-Pin TQFP
Commercial Temp
Industrial Temp
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz167 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8640Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-300 -250 -200 -167 Unit
2.3 2.5 3.0 3.5 ns
3.3 4.0 5.0 6.0 ns
400 340 290 260 mA
480 410 350 305 mA
5.5 6.5 7.5 8.0 ns
5.5 6.5 7.5 8.0 ns
285 245 220 210 mA
330 280 250 240 mA
*All GSI Technology packages are at least 5/6 RoHS compliant.
Packages listed with the additional “G” designator are 6/6 RoHS compliant.
Rev: 1.01 1/2006
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology




GSI Technology

GS8640Z18T-250 Datasheet Preview

GS8640Z18T-250 Datasheet

72Mb Pipelined and Flow Through Synchronous NBT SRAM

No Preview Available !

www.DataSheet4U.com
GS8640Z18T Pinout
Product Preview
GS8640Z18/36T-300/250/200/167
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
VDD
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
2M x 18
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.01 1/2006
2/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology


Part Number GS8640Z18T-250
Description 72Mb Pipelined and Flow Through Synchronous NBT SRAM
Maker GSI Technology
Total Page 25 Pages
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