* FT pin for user-configurable flow through or pipeline operation
* Single Cycle Deselect (SCD) operation
* 2.5 V or 3.3 V +10%/
  –10% core powe.

* JEDEC-standard 100-lead TQFP package
* RoHS-compliant 100-lead TQFP package available Functional Description A.

Applications The GS864018/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supportin.

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