* FT pin for user-configurable flow through or pipelined operation
* Single Cycle Deselect (SCD) operation
* 3.3 V ±10% core power supply
* 2.5 V or 3.3 V.

* JEDEC-standard 119-bump BGA package
* RoHS-compliant 119-bump BGA package Functional Description Applications .

Applications The GS84018/32/36C is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address.

GS84018CGT

GS84018CB

GS84018AB

GS84018AGB

GS84018AGT

GS84018AT

GS84032AB

GS84032AGB

GS84032AGT

GS84032AT

GS84032CB

GS84032CGB

GS84032CGT

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