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GS8342S18BGD - 36Mb SigmaSIO DDR-II Burst of 2 SRAM

This page provides the datasheet information for the GS8342S18BGD, a member of the GS8342S08BD 36Mb SigmaSIO DDR-II Burst of 2 SRAM family.

Datasheet Summary

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

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Datasheet preview – GS8342S18BGD

Datasheet Details

Part number GS8342S18BGD
Manufacturer GSI Technology
File Size 368.14 KB
Description 36Mb SigmaSIO DDR-II Burst of 2 SRAM
Datasheet download datasheet GS8342S18BGD Datasheet
Additional preview pages of the GS8342S18BGD datasheet.

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Full PDF Text Transcription

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GS8342S08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaSIO DDR-IITM Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
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