GS8342S09BD
Features
- Simultaneous Read and Write Sigma SIO™ Interface
- JEDEC-standard pinout and package
- Dual Double Data Rate interface
- Byte Write controls sampled at data-in time
- DLL circuitry for wide output data valid window and future frequency scaling
- Burst of 2 Read and Write
- 1.8 V +100/- 100 m V core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ mode pin for programmable output drive strength
- IEEE 1149.1 JTAG-pliant Boundary Scan
- 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
- Ro HS-pliant 165-bump BGA package available
Sigma SIO™ Family Overview
GS8342S08/09/18/36BD are built in pliance with the Sigma SIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are...
