* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Write controls sampled at .

where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized .

Table Symbol SA NC R W BW Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Write BW0
  –BW3 Synchronous Byte Writes NW0
  –NW1 Nybble Write Control Pin K Input Clock.

GS8342Q36E-200

GS8342Q36E-250

GS8342Q36E-300

GS8342Q36AE

GS8342Q36BD-250

GS8342Q36BD-300

GS8342Q36BD-333

GS8342Q36BD-357

GS8342Q37BD

GS8342Q37BGD

GS8342Q07BD

GS8342Q07BGD

GS8342Q08AE

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