* 2.5 Clock Latency
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Wr.

where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized.

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0
  –BW3 Synchronous Byte Writes Input Active Low NW0
  .

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