GS8342DT19BD Datasheet PDF - GSI Technology 36Mb SigmaQuad-II+ Burst of 4 SRAM Specs

GS8342DT19BD - 36Mb SigmaQuad-II+ Burst of 4 SRAM

This page provides the datasheet information for the GS8342DT19BD, a member of the GS8342DT07BD-450 36Mb SigmaQuad-II+ Burst of 4 SRAM family.

Datasheet Summary

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0 BW3 Synchronous Byte Writes Input Active Low NW0 NW1 Synchronous Nybble Writes Input Active Low (x8 onl

Features

2.0 Clock Latency.
Simultaneous Read and Write SigmaQuad™ Interface.
JEDEC-standard pinout and package.
Dual Double Data Rate interface.
Byte Write controls sampled at data-in time.
Burst of 4 Read and Write.
Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
1.8 V +100/.
100 mV core power supply.
1.5 V or 1.8 V HSTL Interface.
Pipelined read operation.

Datasheet Details

Part number	GS8342DT19BD
Manufacturer	GSI Technology
File Size	280.62 KB
Description	36Mb SigmaQuad-II+ Burst of 4 SRAM
Datasheet	GS8342DT19BD Datasheet
Additional preview pages of the GS8342DT19BD datasheet.

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Full PDF Text Transcription

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GS8342DT07/10/19/37BD-450/400/350/333/300 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaQuad-II+TM Burst of 4 SRAM 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.

Published: Oct 13, 2016 |