* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Write controls sampled at .

where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized .

Table Symbol SA NC R W BW0
  –BW3 NW0
  –NW1 K K C C TMS TDI TCK TDO VREF ZQ Qn Dn Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read .

GS8342D36E-200

GS8342D36E-250

GS8342D36E-300

GS8342D36E-333

GS8342D36AE

GS8342D36BD

GS8342D37BD

GS8342D37BGD

GS8342D38BD

GS8342D38BGD

GS8342D06BD

GS8342D06BGD

GS8342D07BD

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