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GS832272-xxxV Datasheet Preview

GS832272-xxxV Datasheet

36Mb S/DCD Sync Burst SRAMs

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GS832272(C)-xxxV
209-Pin BGA
Commercial Temp
Industrial Temp
512K x 72
36Mb S/DCD Sync Burst SRAMs
250 MHz133 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
• RoHS-compliant package available
Functional Description
Applications
The GS832272-xxxV is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832272-xxxV is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Core and Interface Voltages
The GS832272-xxxV operates on a 1.8 V or 2.5 V power supply.
All inputs are 1.8 V or 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
circuits and are 1.8 V or 2.5 V compatible.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
tKQ
tCycle
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
Curr (x72) 440 410 370 320 300 265 mA
tKQ
tCycle
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
Curr (x72) 315 295 265 255 240 230 mA
Rev: 1.08 10/2014
1/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology




GSI Technology

GS832272-xxxV Datasheet Preview

GS832272-xxxV Datasheet

36Mb S/DCD Sync Burst SRAMs

No Preview Available !

GS832272(C)-xxxV
209-Bump BGA—x72 Common I/O—Top View (Package C)
1 2 3 4 5 6 7 8 9 10 11
A DQG DQG A
E2 ADSP ADSC ADV
E3
A DQB DQB A
B
DQG DQG
BC
BG
NC
BW
A
BB BF DQB DQB B
C
DQG DQG
BH
BD
NC
E1
NC
BE
BA DQB DQB
C
D DQG DQG VSS NC NC G GW NC VSS DQB DQB D
E
DQPG DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
E
F DQC DQC VSS VSS VSS ZQ VSS VSS VSS DQF DQF F
G
DQC
DQC VDDQ VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQF
DQF
G
H DQC DQC VSS VSS VSS MCL VSS VSS VSS DQF DQF H
J
DQC
DQC VDDQ VDDQ
VDD
MCL
VDD
VDDQ
VDDQ
DQF
DQF
J
K NC NC CK NC VSS MCL VSS NC NC NC NC K
L
DQH
DQH
VDDQ
VDDQ
VDD
FT
VDD
VDDQ
VDDQ
DQA
DQA
L
M DQH DQH VSS VSS VSS MCL VSS VSS VSS DQA DQA M
N
DQH
DQH VDDQ VDDQ
VDD
SCD
VDD
VDDQ
VDDQ
DQA
DQA
N
P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA P
R
DQPD DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
DQPE
R
T
DQD DQD VSS
NC
NC LBO NC
NC VSS DQE DQE
T
U
DQD DQD
NC
A
A
A
A
A
A DQE DQE U
V DQD DQD A A A A1 A A A DQE DQE V
W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.08 10/2014
2/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology


Part Number GS832272-xxxV
Description 36Mb S/DCD Sync Burst SRAMs
Maker GSI Technology
Total Page 30 Pages
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