* IEEE 1149.1 JTAG-compatible Boundary Scan
* 2.5 V or 3.3 V +10%/
  –10% core power supply
* 2.5 V or 3.3 V I/O supply
* LBO pin for Linear .

* JEDEC-standard 165-bump FP-BGA package
* Pb-Free 165-bump BGA package available Functional Description Applica.

Applications The GS832118/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds a.

GS832136E-V

GS832136GE

GS832136GE-V

GS832132E

GS832132E-V

GS832132GE

GS832132GE-V

GS832118E

GS832118E-V

GS832118GE

GS832118GE-V

GS8321E18E

GS8321E18E-V

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