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GS8182T18BD - 18Mb SigmaDDR-II Burst of 2 SRAM

Download the GS8182T18BD datasheet PDF. This datasheet also covers the GS8182T08BD variant, as both devices belong to the same 18mb sigmaddr-ii burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Simultaneous Read and Write SigmaDDR-II™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36 and x18) and Nybble Write (x8) function.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for pro.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8182T08BD-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8182T18BD
Manufacturer GSI Technology
File Size 469.87 KB
Description 18Mb SigmaDDR-II Burst of 2 SRAM
Datasheet download datasheet GS8182T18BD Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS8182T08/09/18/36BD-400/375/333/300/250/200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb SigmaDDR-II™ Burst of 2 SRAM 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
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