GS8170LW72C-333 Datasheet, GSI Technology

* Late Write mode, Pipelined Read mode
* JEDEC-standard SigmaRAM™ pinout and package
* 1.8 V +150/
  –100 mV core power supply
* 1.8 V CMOS I.

and in Flow Through mode NBT SRAMs SigmaRAM Late Write with Pipelined Read Read A CK Address ADV E1 Bx W DQ CQ Q(A) D(B.

200 MHz
  –333 MHz 1.8 V VDD 1.8 V I/O SigmaRAM Family Overview GS8170LW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very lo.