* Double Late Write mode, Pipelined Read mode
* JEDEC-standard SigmaRAM™ pinout and package
* 1.8 V +150/
  –100 mV core power supply
* 1.8 V.

Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature .

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