GS816272C
Features
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-patible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V or 3.3 V +10%/- 10% core power supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 209-bump BGA package
Functional Description
Applications The GS816272C is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting...
