* FT pin for user-configurable flow through or pipeline operation
* Single/Dual Cycle Deselect selectable
* IEEE 1149.1 JTAG-compatible Boundary Scan
* ZQ.

* JEDEC-standard 209-bump BGA package Functional Description Applications The GS816272C is an 18,874,368-bit high pe.

Applications The GS816272C is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high .

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