900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






GSI Technology

GS8161Z36BT-xxxV Datasheet Preview

GS8161Z36BT-xxxV Datasheet

18Mb Pipelined and Flow Through Synchronous NBT SRAM

No Preview Available !

Preliminary
GS8161ZxxB(T/D)-xxxV
100-Pin TQFP & 165-Bump BGA 18Mb Pipelined and Flow Through
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
250 MHz150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
• RoHS-compliant TQFPand BGA packages available
Functional Description
The GS8161ZxxB(T/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161ZxxB(T/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8161ZxxB(T/D)-xxxV is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 100-pin TQFP and 165-bump FP-BGA packages.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-250 -200 -150 Unit
tKQ(x18/x36)
tCycle
3.0 3.0 3.8 ns
4.0 5.0 6.7 ns
Curr (x18)
Curr (x32/x36)
280 230 185 mA
330 270 210 mA
tKQ
tCycle
5.5 6.5 7.5 ns
5.5 6.5 7.5 ns
Curr (x18)
Curr (x32/x36)
210 185 170 mA
240 205 190 mA
Rev: 1.01a 6/2006
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology




GSI Technology

GS8161Z36BT-xxxV Datasheet Preview

GS8161Z36BT-xxxV Datasheet

18Mb Pipelined and Flow Through Synchronous NBT SRAM

No Preview Available !

GS8161Z18BT-xxxV Pinout (Package T)
Preliminary
GS8161ZxxB(T/D)-xxxV
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
1M x 18
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA5
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.01a 6/2006
2/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology


Part Number GS8161Z36BT-xxxV
Description 18Mb Pipelined and Flow Through Synchronous NBT SRAM
Maker GSI Technology
Total Page 30 Pages
PDF Download

GS8161Z36BT-xxxV Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 GS8161Z36BT-xxxV 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GSI Technology





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy