GS8161E18B datasheet, srams equivalent, GSI Technology

Features and benefits

* FT pin for user-configurable flow through or pipeline operation
* Dual Cycle Deselect (DCD) operation
* IEEE 1149.1 JTAG-compatible Boundary Scan
* 2.5 .

Application

* JEDEC-standard 100-lead TQFP package
* RoHS-compliant 100-lead TQFP and 165-bump BGA packages available 1M x .

Description

Applications The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performanc.

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