* IEEE 1149.1 JTAG-compatible Boundary Scan
* 1.8 V or 2.5 V core power supply
* 1.8 V or 2.5 V I/O supply
* LBO pin for Linear or Interleaved Burst mode .

* JEDEC-standard 165-bump BGA package
* RoHS-compliant 100-pin TQFP and 165-bump BGA packages available Function.

Applications The GS8161xxD(GT/D)-xxxV is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now f.

Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy   |   Purchase of parts