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GSI Technology

GS8160F18DGT Datasheet Preview

GS8160F18DGT Datasheet

18Mb Sync Burst SRAMs

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GS8160F18/32/36DGT-6.5/7.5
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
6.5 ns – 7.5 ns
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• Flow Through mode operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS8160F18/32/36DGT is an 18,874,368-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160F18/32/36DGT operates on a 3.3 V or 2.5 V
power supply. All input are 3.3 V and 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 3.3 V and 2.5 V
compatible.
Parameter Synopsis
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-6.5 -7.5 Unit
6.5 7.5 ns
6.5 7.5 ns
205 190 mA
225 205 mA
Rev: 1.01 10/2013
1/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology




GSI Technology

GS8160F18DGT Datasheet Preview

GS8160F18DGT Datasheet

18Mb Sync Burst SRAMs

No Preview Available !

GS8160F18D 100-Pin TQFP Pinout
GS8160F18/32/36DGT-6.5/7.5
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
1M x 18
72
71
11 Top View
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.01 10/2013
2/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2013, GSI Technology


Part Number GS8160F18DGT
Description 18Mb Sync Burst SRAMs
Maker GSI Technology
Total Page 22 Pages
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