* 2.0 Clock Latency
* Simultaneous Read and Write SigmaDDR™ Interface
* Common I/O bus
* JEDEC-standard pinout and package
* Double Data Rate interfac.

Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs a.

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read Input High: Read Low: Write BW0
  –BW3 Synchronous Byte Writes Input Active Low LD Synchronous Load Pin Input Active Low K.

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