Datasheet4U Logo Datasheet4U.com

GS81302R36E - 144Mb SigmaDDR-II Burst of 4 SRAM

This page provides the datasheet information for the GS81302R36E, a member of the GS81302R08E-375 144Mb SigmaDDR-II Burst of 4 SRAM family.

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R/W Synchronous Read/Write Input Read: Active High Write: Active Low BW0 BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0 NW1 Nybble Write Control Pin Input Active Low

Features

  • Simultaneous Read and Write SigmaDDR™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36 and x18) and Nybble Write (x8) function.
  • Burst of 4 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for progra.

📥 Download Datasheet

Datasheet preview – GS81302R36E

Datasheet Details

Part number GS81302R36E
Manufacturer GSI Technology
File Size 460.25 KB
Description 144Mb SigmaDDR-II Burst of 4 SRAM
Datasheet download datasheet GS81302R36E Datasheet
Additional preview pages of the GS81302R36E datasheet.

📁 Similar Datasheet

  • GS810C - Microprocessor Reset Monitors (Vishay Siliconix)
  • GS816118 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816118B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS816132 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816132B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS816136 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816136B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS8161E18 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
  • GS8161E32 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
  • GS8161E36 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
Other Datasheets by GSI Technology

Full PDF Text Transcription

Click to expand full text
GS81302R08/09/18/36E-375/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II Burst of 4 SRAM 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
Published: |