Download the GS81302R18GE datasheet PDF.
This datasheet also covers the GS81302R08E-375 variant, as both devices belong to the same 144mb sigmaddr-ii burst of 4 sram family and are provided as variant models within a single manufacturer datasheet.
Description
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input
R/W
Synchronous Read/Write
Input
Read: Active High Write: Active Low
BW0
BW3
Synchronous Byte Writes
Input
Active Low x18/x36 only
NW0
NW1
Nybble Write Control Pin
Input
Active Low
Features
- Simultaneous Read and Write SigmaDDR™ Interface.
- Common I/O bus.
- JEDEC-standard pinout and package.
- Double Data Rate interface.
- Byte Write (x36 and x18) and Nybble Write (x8) function.
- Burst of 4 Read and Write.
- 1.8 V +100/.
- 100 mV core power supply.
- 1.5 V or 1.8 V HSTL Interface.
- Pipelined read operation with self-timed Late Write.
- Fully coherent read and write pipelines.
- ZQ pin for progra.
GS81302R18GE Datasheet
