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GS81284Z18B-xxxV Datasheet Preview

GS81284Z18B-xxxV Datasheet

144Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS81284Z18/36B-xxxV
119-Bump BGA
Commercial Temp
Industrial Temp
144Mb Pipelined and Flow Through
Synchronous NBT SRAM
200 MHz167 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 8Mb, 36Mb, and 72Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-BGA package
• RoHS-compliant 119-BGA packages available
Functional Description
The GS81284Z18/36(B)-xxxV is a 144Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS81284Z18/36-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS81284Z18/36-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump p BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-200 -167 Unit
tKQ
tCycle
3.0 3.4 ns
5.0 6.0 ns
Curr (x18)
Curr (x36)
420 385 mA
480 430 mA
tKQ
tCycle
7.5 8.0 ns
7.5 8.0 ns
Curr (x18)
Curr (x36)
340 330 mA
370 360 mA
Rev: 1.02 7/2010
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology




GSI Technology

GS81284Z18B-xxxV Datasheet Preview

GS81284Z18B-xxxV Datasheet

144Mb Pipelined and Flow Through Synchronous NBT SRAM

No Preview Available !

GS81284Z18/36B-xxxV
GS81284Z36B-xxxV Pad Out–119-Bump BGA—Top View
1234567
A VDDQ A A A A A VDDQ A
B NC E2 A ADV A E3 NC B
C NC A
A VDD A
A NC C
D
DQC DQPC
VSS
ZQ
VSS DQPB DQB
D
E
DQC DQC
VSS
E1
VSS DQB DQB
E
F
VDDQ
DQC
VSS
G
VSS
DQB
VDDQ
F
G
DQC DQC
BC
A
BB DQB DQB
G
H
DQC DQC
VSS
W
VSS DQB DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD VDDQ
J
K
DQD DQD
VSS
CK
VSS DQA DQA
K
L
DQD DQD
BD
NC
BA DQA DQA
L
M
VDDQ
DQD
VSS
CKE
VSS
DQA
VDDQ
M
N
DQD DQD
VSS
A1
VSS DQA DQA
N
P
DQD DQPD
VSS
A0
VSS DQPA DQA
P
R A A LBO VDD FT A NC R
T NC A A A A A ZZ T
U
VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.02 7/2010
2/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology


Part Number GS81284Z18B-xxxV
Description 144Mb Pipelined and Flow Through Synchronous NBT SRAM
Maker GSI Technology
Total Page 28 Pages
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