GS81280E36GT
Features
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 1.8 V or 2.5 V +10%/- 10% core power supply
- 1.8 V or 2.5 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- Ro HS-pliant 100-lead TQFP package
Functional Description
Applications The GS81280E18/32/36GT-xxx V is a 150,994,944-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds...
