* FT pin for user-configurable flow through or pipeline operation
* Dual Cycle Deselect (DCD) operation
* 1.8 V or 2.5 V +10%/
  –10% core power .

* RoHS-compliant 100-lead TQFP package Functional Description Applications The GS81280E18/32/36GT-xxxV is a 150,994,.

Applications The GS81280E18/32/36GT-xxxV is a 150,994,944-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device no.

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