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GS72116AGP Datasheet Preview

GS72116AGP Datasheet

2Mb Asynchronous SRAM

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GS72116AGP/U
TSOP, FP-BGA
Commercial Temp
Industrial Temp
128K x 16
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: 40° to 85°C
• Package line up
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA and 400 mil TSOP Type-II packages.
Pin Descriptions
Symbol
A0A16
DQ1DQ16
CE
LB
UB
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Fine Pitch BGA 128K x 16-Bump Configuration
123456
A LB OE A0 A1 A2 NC
B DQ16 UB A3 A4 CE DQ1
C DQ14 DQ15 A5 A6 DQ2 DQ3
D VSS DQ13 NC A7 DQ4 VDD
E VDD DQ12 NC A16 DQ5 VSS
F DQ11 DQ10 A8 A9 DQ7 DQ6
G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
TSOP-II 128K x 16-Pin Configuration
A4 1
A3 2
A2 3
A1 4
Top view
A0 5
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS
DQ5
12
13
TSOP II
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ16
37 DQ15
36 DQ14
35
34
33
32
31
DQ13
VSS
VDD
DQ12
DQ11
30 DQ10
29 DQ9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Package TP
Rev: 1.11 1/2013
1/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology




GSI Technology

GS72116AGP Datasheet Preview

GS72116AGP Datasheet

2Mb Asynchronous SRAM

No Preview Available !

Block Diagram
GS72116AGP/U
A0 Row
Decoder
Address
Input
Buffer
A16
CE
WE
OE
Control
UB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
Truth Table
CE OE WE LB UB
HXXXX
LL
L LHLH
HL
LL
LXLLH
HL
LHHXX
L X XHH
Note:
X: “H” or “L”
DQ1 to DQ8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ9 to DQ16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
VDD Current
ISB1, ISB2
IDD
Rev: 1.11 1/2013
2/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology


Part Number GS72116AGP
Description 2Mb Asynchronous SRAM
Maker GSI Technology
Total Page 13 Pages
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