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CDP1852 Datasheet Preview

CDP1852 Datasheet

Byte-Wide Input/Output Port

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP1852, CDP1852C
CSI!~
MODE
OIO
000
OIl
001
OI2
002
0I3
003
CLOCK
VSS
I • 24 VOO
2 23 SR/SR
3 22 0I7
4 21 007
I.5 20 OI6
6 19 006
DI5
17 DOS
9 16 OI4
10 15 004
II I. CLEAR
12 13 CS2
TOP VIEW
92C5-27572
CDP1852, CDP1852C
TERMINAL ASSIGNMENT
Byte-Wide Input/Output Port
Features:
• Static silicon-gate CMOS circuitry
• Parallel B-bit data register and buffer
• Handshaking via service request flip-flop
• Low quiescent and operating power
• Interfaces directly with CDP1BOO-series
microprocessors
• Single voltage supply
• Full military temperature
range (-55°C to +125°C)
The ACA-CDP1852 and CDP1852C are parallel, 8-bit,
mode-programmable input/output ports. They are compat-
ible and will interface directly with CDP1800,eries micro-
processors. They are also useful as 8-bit address latches
when used with the CDP1800 multiplexed address bus and
as liD ports in general-purpose applications.
The mode control is used to program the device as an input
port (mode=O) or as an output port (mode=1). The Sl'!/SA
output can be used as a signal to indicate when data is ready
to be transferred. In the input mode, a peripheral device can
strobe data into the CDP1852, and a microprocessor can
read that data by device selection. In the output mode, a
microprocessor strobes data Into the CDP1852, and hand-
shaking is established with a peripheral device when the
CDP1852 is deselected.
In the input mode, data at the data-In terminals (D10-D17) is
strobed into the port's 8-bit register by a high (1) level on the
clock line. The negative high-to-Iow transition of the clock
latches the data in the register and sets the service request
output low (SR/SA=O). When CS1/CS1 and CS2 are high
(CS1/~ and CS2=1), the 3-state output drivers are
enabled and data in the8-bit register appear at the data-out
terminals (DOO-D07). When either CS1/CS1 or CS2 goes
low (CS1/CS1 or CS2=O), the data-out terminals are tri-
stated and the service request output returns high
(Sl'!/SA=1).
In the output mode, the output drivers are enabled at all
times. Data at the data-in terminals (D10-D17) is strobed
into the 8-bit register when CS1/CS1 is low (CS1/CS1=O)
and CS2 and the clock are high (1), and are present at the
data-out terminals (DOO-D07). The negative high-to-Iow
transition of the clock latches the data in the register. The
SAlSA output goes high (SR/SR=1) when the device is
deselected (CS1/CS1=1 or CS2=O) and returns low
(SR/SA=O) on the following trailing edge of the clock.
AODR BUS
TPA
----
----
-
~
ADDR BUS
TPA
NO-N2 MRO
TPB
0
I"""""'
~
~CONTROl>ROM
RAM
CPU
CDPIB02
seD SCI
INTERRUPT
'I/O
CDP18521'
MR5
MRO
OMA-IN MA-OUT
CEO
MWR
EFt EF4
[I II
Jf
BIDIRECTIONAL DATA BUS
l2:"'-?~'-'
Fig. 1 - Typical CDP1802 microprocessor system.
File Number 1166
_________________________________________________________ 375




GE

CDP1852 Datasheet Preview

CDP1852 Datasheet

Byte-Wide Input/Output Port

No Preview Available !

CMOS Peripherals
CDP1852, CDP1852C
A CLEAR control is provided for resetting
the port's register (DOO-D07 = 0) and ser-
vice request flip-flop (in~t mode: SRI
SR=1 and output mode: S"R/SR=O).
The CDP1852 is functionally identical to
the CDP1852C. The CDP1852 has a recom-
mended operating voltage range of 4 to 10.5
volts, and the CDP1852C has a recom-
mended operating voltage range of 4 to 6.5
volts.
The CDP1852 and CDP1852C are supplied
in 24-lead, hermetic, dual-in-line ceramic
packages (D suffix), in 24-lead dual-in-line
plastic packages (E suffix). The CDP1852C
is also available in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Vollage referenced 10 Vss Terminal
CDP1852 ...................................................... ............... -0.510+11 V
CDPI852C ...................................................................•• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................-0.5 to Voo + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................± 10 mA
POWER DISSIPATION PER PACKAGE (Po).
For T. = -40 to +60°C (PACKAGE TYPE E) ......................................•.... 500 mW
For T. = + 60 to + 85° C (PACKAGE TYPE E) ............ Derate Linearly at 12 mW/o C to 200 mW
For T. = -55 to + 100°C (PACKAGE TYPE D) .......................................... 500 mW
mwrcFor T. = + 100 to + 125°C (PACKAGE TYPE D) ......... Derate Linearly at 12
to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPES D, H ..................................................... -55 to + 125°C
PACKAGE TYPE E .............................................................. -40 to + 85° C
STORAGE TEMPERATURE RANGE (T..,) ......................................... -65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING).
At dlslance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 10 s max ...................+ 265° C
RECOMMENDED OPERATING CONDITIONS at T. = Full Package Temperature Range.
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
LIMITS
CDP1852
CDP1852C
Min.
Max.
Min.
Max.
4 10.5 4 6.5
Vss VDD Vss VDD
UNITS
V
017 - " L ._ _--.J
000
001
002
00'
00'
00.
006
L-_--'-007
PI
P23 f---':::'-l--"""----j
92C8- 27574R I
Fig 2 - Block diagram of CDP1852.
376 _________________________________________________________________


Part Number CDP1852
Description Byte-Wide Input/Output Port
Maker GE
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CDP1852 Datasheet PDF






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